View DS1340Z-3TAMPR_5001897.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds1340 is a real-time clock (rtc)/calendar that is pin compatible and functionally equivalent to the st m41t00, including the software clock calibration. the device additionally provides trickle-charge capability on the v backup pin, a lower timekeeping voltage, and an oscillator stop flag. block access of the register map is identical to the st device. two additional regis- ters, which are accessed individually, are required for the trickle charger and flag. the clock/calendar pro- vides seconds, minutes, hours, day, date, month, and year information. a built-in power-sense circuit detects power failures and automatically switches to the back- up supply. reads and writes are inhibited while the clock continues to run. the device is programmed seri- ally through an i 2 c * bidirectional bus. applications portable instruments point-of-sale equipment medical equipment telecommunications features ? enhanced second source for the st m41t00 ? available in a surface-mount package with an integrated crystal (ds1340c) ? fast (400khz) i 2 c interface ? software clock calibration ? rtc counts seconds, minutes, hours, day, date, month, and year ? automatic power-fail detect and switch circuitry ? trickle-charge capability ? low timekeeping voltage down to 1.3v ? three operating voltage ranges (1.8v, 3v, and 3.3v) ? oscillator stop flag ? available in 8-pin sop or so packages ? underwriters laboratory (ul) recognized ds1340 i 2 c rtc with trickle charger ______________________________________________ maxim integrated products 1 ordering information 4 cpu v cc v cc v cc 5 6 8 12 sda scl gnd x2 x1 v cc c1 r pu r pu crystal ft/out v backup 3 7 r pu = t r / c b ds1340 t ypical operating circuit rev 4; 3/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package top mark ? ds1340z-18 -40? to +85? 8 so (0.150in) d1340-18 ds1340z-3 -40? to +85? 8 so (0.150in) ds1340-3 ds1340z-33 -40? to +85? 8 so (0.150in) d1340-33 ds1340u-18 -40? to +85? 8 ?op 1340a1-18 ds1340u-3 -40? to +85? 8 ?op 1340a1-3 ds1340u-33 -40? to +85? 8 ?op 1340a1-33 ds1340c-18 -40? to +85? 16 so 1340c-18 ds1340c-3 -40? to +85? 16 so 1340c-3 ds1340c-33 -40? to +85? 16 so 1340c-33 ds1340z-18+ -40? to +85? 8 so (0.150in) d1340-18 ds1340z-3+ -40? to +85? 8 so (0.150in) ds1340-3 ds1340z-33+ -40? to +85? 8 so (0.150in) d1340-33 ds1340u-18+ -40? to +85? 8 ?op 1340a1-18 ds1340u-3+ -40? to +85? 8 ?op 1340a1-3 ds1340u-33+ -40? to +85? 8 ?op 1340a1-33 ds1340c-18# -40? to +85? 16 so 1340c-18 ds1340c-3# -40? to +85? 16 so 1340c-3 ds1340c-33# -40? to +85? 16 so 1340c-33 * purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. pin configurations appear at end of data sheet. + denotes a lead-free/rohs-compliant device. # denotes a rohs-compliant device that may include lead that is exempt under rohs requirements. the lead finish is jesd97 category e3, and is compatible with both lead-based and lead- free soldering processes. ? a "+" anywhere on the top mark denotes a lead-free device. a "#" denotes a rohs-compliant device.
ds1340 i 2 c rtc with trickle charger 2 _____________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc pin relative to ground .....-0.3v to +6.0v voltage range on sda, scl, and ft/out relative to ground..................................-0.3v to (v cc + 0.3v) operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature range............................see ipc/jedec j-std-020 specification ac electrical characteristics (v cc = v cc min to v cc max , t a = -40? to +85?, unless otherwise noted.) (note 1, figure 1) parameter symbol conditions min typ max units standard mode 0 100 scl clock frequency f scl fast mode 100 400 khz standard mode 4.7 bus free time between stop and start conditions t buf fast mode 1.3 ? standard mode 4.0 hold time (repeated) start condition (note 2) t hd:sta fast mode 0.6 ? standard mode 4.7 low period of scl clock t low fast mode 1.3 ? standard mode 4.0 high period of scl clock t high fast mode 0.6 ? standard mode 0 0.9 data hold time (notes 3, 4) t hd:dat fast mode 0 0.9 ? standard mode 250 data setup time (note 5) t su:dat fast mode 100 ns standard mode 4.7 start setup time t su:sta fast mode 0.6 ? standard mode 20 + 0.1c b 1000 rise time of sda and scl signals (note 6) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 fall time of sda and scl signals (note 6) t f fast mode 20 + 0.1c b 300 ns standard mode 4.7 setup time for stop condition t su:sto fast mode 0.6 ? capacitive load for each bus line c b (note 6) 400 pf i/o capacitance (scl, sda) c i/o 10 pf pulse width of spikes that must be suppressed by the input filter t sp fast mode 30 ns oscillator stop flag (osf) delay t osf (note 7) 100 ms
ds1340 i 2 c rtc with trickle charger _____________________________________________________________________ 3 recommended dc operating conditions (v cc = v cc min to v cc max , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units ds1340-18 1.71 1.8 1.89 ds1340-3 2.7 3.0 3.3 supply voltage (note 8) v cc ds1340-33 2.97 3.3 5.5 v input logic 1 (sda, scl) v ih (note 8) 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl) v il (note 8) -0.3 +0.3 x v cc v supply voltage, pullup (ft/out, sda, scl), v cc = 0v v pu (note 8) 5.5 v ds1340-18 1.3 3.7 ds1340-3 1.3 3.7 backup supply voltage (note 8) v backup ds1340-33 1.3 5.5 v r1 (notes 9, 10) 250 r2 (note 11) 2000 trickle-charge current-limiting resistors r3 (note 12) 4000 ? ds1340-18 1.51 1.6 1.71 ds1340-3 2.45 2.6 2.7 power-fail voltage (note 8) v pf ds1340-33 2.70 2.88 2.97 v input leakage (scl, clk) i li -1 +1 ? i/o leakage (sda, ft/out) i lo -1 +1 ? v cc > 2v; v ol = 0.4v 3.0 sda logic 0 output i olsda 1.7v < v cc < 2v; v ol = 0.2 x v cc 3.0 ma v cc > 2v; v ol = 0.4v 3.0 1.7v < v cc < 2v; v ol = 0.2 x v cc 3.0 ma ft/out logic 0 output i olsqw 1.3v < v cc < 1.7v; v ol = 0.2x v cc 250 ? ds1340-18 72 150 ds1340-3 108 200 active supply current (note 13) i cca ds1340-33 192 300 ? ds1340-18 60 100 ds1340-3 81 125 standby current (note 14) i ccs ds1340-33 100 150 ? v backup leakage current i backuplkg v backup = 3.7v 100 na dc electrical characteristics (v cc = 0v, v backup = 3.7v, t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units i backup1 osc on, ft = 0 (note 15) 800 1150 i backup2 osc on, ft = 1 (note 15) 850 1250 v backup current i backup3 osc on, ft = 0, v backup = 3.0v, t a = +25?c (notes 15, 16) 800 1000 na v backup data-retention current i backupdr osc off 25.0 100 na
ds1340 i 2 c rtc with trickle charger 4 _____________________________________________________________________ power-up/power-down characteristics (t a = -40? to +85?) (figure 2) parameter symbol conditions min typ max units recovery at power-up t rec (note 17) 2 ms v cc fall time; v pf(max) to v pf(min) t vccf 300 ? v cc rise time; v pf(min) to v pf(max) t vccr 0s warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. note 1: limits at -40? are guaranteed by design and not production tested. note 2: after this period, the first clock pulse is generated. note 3: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 4: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 5: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat to 250ns must be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 6: c b ?otal capacitance of one bus line in pf. note 7: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the 0v v cc v ccmax and 1.3v v bat 3.7v range. note 8: all voltages are referenced to ground. note 9: measured at v cc = typ, v backup = 0v, register 08h = a5h. note 10: the use of the 250 ? trickle-charge resistor is not allowed at v cc > 3.63v and should not be enabled. note 11: measured at v cc = typ, v backup = 0v, register 08h = a6h. note 12: measured at v cc = typ, v backup = 0v, register 08h = a7h. note 13: i cca ?cl clocking at max frequency = 400khz. note 14: specified with i 2 c bus inactive. note 15: measured with a 32.768khz crystal attached to the x1 and x2 pins. note 16: limits at +25? are guaranteed by design and not production tested. note 17: this delay applies only if the oscillator is enabled and running. if the oscillator is disabled or stopped, no power-up delay occurs. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 1. data transfer on i 2 c serial bus
ds1340 i 2 c rtc with trickle charger _____________________________________________________________________ 5 outputs v cc v pf(max) inputs high-z rst don't care v alid recognized recognized v alid v pf(min) t rst t rpu t r t f v pf v pf figure 2. power-up/power-down timing i ccsa vs. v cc ft = 0 ds1340 toc01 v cc (v) supply current ( a) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 50 100 150 200 250 0 1.0 5.5 25 50 75 100 125 150 0 i ccs vs. v cc ft = 0 ds1340 toc02 v cc (v) supply current ( a) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5.5 -1.8v -3.0v -3.3v i backup1 (ft = 0) vs. v backup ds1340 toc03 450 500 550 600 650 700 750 800 850 400 v backup (v) supply current (na) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5.5 t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) i backup2 (ft = 1) vs. v backup ds1340 toc04 450 500 550 600 650 700 750 800 850 400 v backup (v) supply current (na) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5.5 ft vs. v backup ds1340 toc06 v backup (v) frequency (hz) 5.0 4.5 1.5 2.0 2.5 3.5 3.0 4.0 511.9965 511.9970 511.9975 511.9980 511.9985 511.9990 511.9995 512.0000 511.9960 1.0 5.5 i backup3 vs. temperature ds1340 toc05 temperature ( c) supply current (na) 60 40 -20 0 20 500 550 600 650 700 750 800 850 -40 80 v backup = 3.0v
ds1340 detailed description the ds1340 is a low-power clock/calendar with a trickle charger. address and data are transferred serially through a i 2 c bidirectional bus. the clock/calendar pro- vides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the ds1340 has a built-in power-sense circuit that detects power fail- ures and automatically switches to the backup supply. power control the power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when vcc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed t rec . i 2 c rtc with trickle charger 6 _____________________________________________________________________ pin description pin 8 16 name function 1 x1 2 x2 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 12.5pf. x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator, x2, is floated if an external oscillator is connected to x1. 3 14 v backup connection for a secondary power supply. for the 1.8v and 3v devices, v backup must be held between 1.3v and 3.7v for proper operation. diodes placed in series between the supply and the input pin may result in improper operation. v backup can be as high as 5.5v on the 3.3v device. this pin can be connected to a primary cell such as a lithium coin cell. additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. ul recognized to ensure against reverse charging when used with a lithium battery (www.maxim-ic.com/qa/info/ul). 4 15 gnd ground 5 16 sda serial data input/output. sda is the data input/output for the i 2 c serial interface. the sda pin is open drain and requires an external pullup resistor. 6 1 scl serial clock input. scl is the clock input for the i 2 c interface and is used to synchronize data movement on the serial interface. 7 2 ft/out frequency test/output. this pin is used to output either a 512hz signal or the value of the out bit. when the ft bit is logic 1, the ft/out pin toggles at a 512hz rate. when the ft bit is logic 0, the ft/out pin reflects the value of the out bit. this open-drain pin requires an external pullup resistor, and operates with either v cc or v backup applied. 8 3 v cc p r i m ar y p ow er s up p l y. w hen vol tag e i s ap p l i ed w i thi n nor m al l i m i ts, the d evi ce i s ful l y accessi b l e and d ata can b e w r i tten and r ead . w h en a b ackup sup p l y i s connected to the d evi ce and v c c i s b el ow v t p , r ead s and w r i tes ar e i nhi b i ted . h ow ever , the ti m ekeep i ng functi on conti nues unaffected b y the l ow er i np ut vol tag e. 4?3 n.c. no connection. must be connected to ground. supply condition read/write access powered by v cc < v pf , v cc < v backup no v bat v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc table 1. power control
oscillator circuit the ds1340 uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 2 specifies several crys- tal parameters for the external crystal. figure 3 shows a functional schematic of the oscillator circuit. if using a crystal with the specified characteristics, the startup time is usually less than one second. clock accuracy the initial clock accuracy depends on the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capaci- tive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit can result in the clock running fast. figure 4 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clocks (www.maxim-ic.com/rtcapps) for detailed information. ds1340c only the ds1340c integrates a standard 32,768hz crystal into the package. typical accuracy with nominal v cc and +25? is approximately +15ppm. refer to application note 58 for information about crystal accu- racy vs. temperature. operation the ds1340 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code fol- lowed by data. subsequent registers can be accessed sequentially until a stop condition is executed. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the regis- ters are maintained from the v backup source until v cc is returned to nominal levels. the functional diagram (figure 5) shows the main elements of the serial rtc. ds1340 i 2 c rtc with trickle charger _____________________________________________________________________ 7 parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45,60** k ? table 2. crystal specifications* * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi- tional specifications. ** a crystal with up to 60k ? esr can be used if the minimum operating voltages on both v cc and v backup are at least 2.0v. countdown chain rtc x1 x2 c l 1 c l 2 crystal rtc registers figure 3. oscillator circuit showing internal bias network crystal x1 x2 gnd local ground plane (layer 2) figure 4. layout example serial bus interface and address register oscillator control logic x2 "c" version only scl sda 512hz mux/buffer ft/out user buffer (7 bytes) clock and calendar registers 32,768hz 1hz x1 power control v cc v backup divider and calibration circuit ds1340 figure 5. functional diagram
ds1340 address map table 3 shows the ds1340 address map. the rtc reg- isters are located in address locations 00h to 06h, and the control register is located at 07h. the trickle-charge and flag registers are located in address locations 08h to 09h. during a multibyte access of the timekeeping registers, when the address pointer reaches 07h?he end of the clock and control register space?t wraps around to location 00h. writing the address pointer to the corresponding location accesses address locations 08h and 09h. after accessing location 09h, the address pointer wraps around to location 00h. on a i 2 c start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of regis- ters. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to reread the registers in case the main registers update during a read. clock and calendar the time and calendar information is obtained by read- ing the appropriate register bytes. table 3 shows the rtc registers. the time and calendar data are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. bit 7 of register 0 is the enable oscillator ( eosc ) bit. when this bit is set to 1, the oscillator is disabled. when cleared to 0, the oscillator is enabled. the initial power-up value of eosc is 0. location 02h is the century/hours register. bit 7 and bit 6 of the century/hours register are the century-enable bit (ceb) and the century bit (cb). setting ceb to logic 1 causes the cb bit to toggle, either from a logic 0 to a logic 1, or from a logic 1 to a logic 0, when the years register rolls over from 99 to 00. if ceb is set to logic 0, cb does not toggle. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchro- nized to the internal registers on any start or stop and when the register pointer rolls over to zero. the time information is read from these secondary registers while the clock continues to run. this eliminates the need to reread the registers in case the internal regis- ters update during a read. the divider chain is reset whenever the seconds regis- ter is written. write transfers occur on the acknowledge from the ds1340. once the divider chain is reset, to avoid rollover issues, the remaining time and date reg- isters must be written within one second. special-purpose registers the ds1340 has three additional registers (control, trickle charger, and flag) that control the rtc, trickle charger, and oscillator flag output. i 2 c rtc with trickle charger 8 _____________________________________________________________________ address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h eosc 10 seconds seconds seconds 00?9 01h x 10 minutes minutes minutes 00?9 02h ceb cb 10 hours hours century/hours 0?; 00?3 03h x x x x x day day 01?7 04h x x 10 date date date 01?1 05h x x x 10 month month month 01?2 06h 10 year year year 00?9 07h out ft s cal4 cal3 cal2 cal1 cal0 control 08h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger 09h osf 0 0 0 0 0 0 0 flag table 3. address map x = read/write bit note: unless otherwise specified, the state of the registers is not defined when power is first applied.
control register (07h) bit 7: output control (out). this bit controls the out- put level of the ft/out pin when the ft bit is set to 0. if ft = 0, the logic level on the ft/out pin is 1 if out = 1 and 0 if out = 0. the initial power-up out value is 1. bit 6: frequency test (ft). when this bit is 1, the ft/out pin toggles at a 512hz rate. when ft is written to 0, the out bit controls the state of the ft/out pin. the initial power-up value of ft is 0. bit 5: calibration sign bit (s). a logic 1 in this bit indi- cates positive calibration for the rtc. a 0 indicates negative calibration for the clock. see the clock calibration section for a detailed description of the bit operation. the initial power-up value of s is 0. bits 4 to 0: calibration bits (cal4 to cal0). these bits can be set to any value between 0 and 31 in binary form. see the clock calibration section for a detailed description of the bit operation. the initial power-up value of cal0?al4 is 0. trickle-charger register (08h) the simplified schematic in figure 6 shows the basic components of the trickle charger. the trickle-charge select (tcs) bits (bits 4?) control the selection of the trickle charger. to prevent accidental enabling, only a pattern on 1010 enables the trickle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. the diode- select (ds) bits (bits 2, 3) select whether or not a diode is connected between v cc and v backup . if ds is 01, no diode is selected; if ds is 10, a diode is selected. the rout bits (bits 0, 1) select the value of the resistor connected between v cc and v backup . table 3 shows the resistor selected by the resistor select (rout) bits and the diode selected by the diode select (ds) bits. warning: the rout value of 250 ? must not be select- ed whenever v cc is greater than 3.63v. the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging (table 4). the maximum charg- ing current can be calculated as illustrated in the fol- lowing example. assume that a 3.3v system power supply is applied to v cc and a super cap is connected to v backup . also assume that the trickle charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculat- ed as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k ? 1.3ma as the super cap charges, the voltage drop between v cc and v backup decreases and therefore the charge current decreases. ds1340 i 2 c rtc with trickle charger _____________________________________________________________________ 9 bit 7 tcs3 1 of 16 select note: only 1010b enables charger 1 of 2 select v cc v backup r1 250 ? tcs 0-3 = trickle-charger select ds 0-1 = diode select tout 0-1 = resistor select r2 2k ? r3 4k ? 1 of 3 select bit 6 tcs2 bit 5 tcs1 bit 4 tcs0 bit 3 ds1 bit 2 ds0 bit 1 rout1 bit 0 rout0 figure 6. trickle charger functional diagram
ds1340 flag register (09h) bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and may be used to judge the validity of the clock and calendar data. this bit is edge triggered and is set to logic 1 when the internal circuitry senses that the oscillator has transi- tioned from a normal run state to a stop condition. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltages present on v cc and v backup are insufficient to support oscillation. 3) the eosc bit is set to 1, disabling the oscillator. 4) external influences on the crystal (e.g., noise, leakage). the osf bit remains at logic 1 until written to logic 0. it can only be written to logic 0. attempting to write osf to logic 1 leaves the value unchanged. bits 6 to 0: all other bits in the flag register read as 0 and cannot be written. clock calibration the ds1340 provides a digital clock calibration feature to allow compensation for crystal and temperature vari- ations. the calibration circuit adds or subtracts counts from the oscillator divider chain at the divide-by-256 stage. the number of pulses blanked (subtracted for negative calibration) or inserted (added for positive cal- ibration) depends upon the value loaded into the five calibration bits (cal4?al0) located in the control reg- ister. adding counts speeds the clock up and subtract- ing counts slows the clock down. the calibration bits can be set to any value between 0 and 31 in binary form. bit 5 of the control register, s, is the sign bit. a value of 1 for the s bit indicates positive calibration, while a value of 0 represents negative cali- bration. calibration occurs within a 64-minute cycle. the first 62 minutes in the cycle can, once per minute, have a one-second interval where the calibration is per- formed. negative calibration blanks 128 cycles of the 32,768hz oscillator, slowing the clock down. positive calibration inserts 256 cycles of the 32,768hz oscillator, speeding the clock up. if a binary 1 is loaded into the calibration bits, only the first two minutes in the 64- minute cycle are modified. if a binary 6 is loaded, the first 12 minutes are affected, and so on. therefore, each calibration step either adds 512 or subtracts 256 oscillator cycles for every 125,829,120 actual 32,678hz oscillator cycles (64 minutes). this equates to +4.068ppm or -2.034ppm of adjustment per calibration step. if the oscillator runs at exactly 32,768hz, each of the 31 increments of the calibration bits would repre- sent +10.7 or -5.35 seconds per month, corresponding to +5.5 or -2.75 minutes per month. for example, if using the ft function, a reading of 512.01024hz would indicate a +20ppm oscillator fre- quency error, requiring a -10(00 1010) value to be loaded in the s bit and the five calibration bits. note: setting the calibration bits does not affect the fre- quency test output frequency. also note that writing to the control register resets the divider chain. i 2 c rtc with trickle charger 10 ____________________________________________________________________ tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 function xxxx00xx disabled xxxx11xx disabled xx x xxx00disabled 10 1 001 01 no diode, 250 ? resistor 10 1 010 01 one diode, 250 ? resistor 10 1 001 10 no diode, 2k ? resistor 10 1 010 10 one diode, 2k ? resistor 10 1 001 11 no diode, 4k ? resistor 10 1 010 11 one diode, 4k ? resistor 00 0 000 00 power-on reset value table 4. trickle-charge register
i 2 c serial data bus the ds1340 supports a bidirectional i 2 c bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiv- ing data as a receiver. the device that controls the message is called a master. the devices that are con- trolled by the master are slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop condi- tions must control the bus. the ds1340 operates as a slave on the i 2 c bus. connections to the bus are made through the open-drain i/o lines sda and scl. within the bus specifications a standard mode (100khz max clock rate) and a fast mode (400khz max clock rate) are defined. the ds1340 works in both modes. the following bus protocol has been defined (figure 7): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are inter- preted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the data line? state from high to low, while the clock line is high, defines a start condition. stop data transfer: a change in the data line? state from low to high, while the clock line is high, defines a stop condition. data valid: the data line? state represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condi- tion and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowl- edge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. ds1340 i 2 c rtc with trickle charger ____________________________________________________________________ 11 stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 7. i 2 c data transfer overview
ds1340 i 2 c rtc with trickle charger 12 ____________________________________________________________________ figures 8 and 9 detail how data transfer is accom- plished on the i 2 c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a num- ber of data bytes. the slave returns an acknowl- edge bit after each received byte. data transfer from a slave transmitter to a mas- ter receiver. the master transmits the first byte (the slave address). the slave then returns an acknowl- edge bit. next follows a number of data bytes trans- mitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. the ds1340 can operate in the following two modes: slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recog- nized as the beginning and end of a serial trans- fer. hardware performs address recognition after reception of the slave address and direction bit. the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7-bit ds1340 address, which is 1101000, followed by the direc- tion bit (r/ w ), which is 0 for a write. after receiving and decoding the slave address byte, the ds1340 outputs an acknowledge on sda. after the ds1340 acknowledges the slave address + write bit, the master transmits a word address to the ds1340. this sets the register pointer on the ds1340, with the ds1340 acknowledging the transfer. the master can then transmit zero or more bytes of data, with the ds1340 acknowledg- ing each byte received. the register pointer incre- ments after each data byte is transferred. the master generates a stop condition to terminate the data write. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direc- tion bit indicates that the transfer direction is reversed. the ds1340 transmits serial data on sda while the serial clock is input on scl. start and stop conditions are recognized as the begin- ning and end of a serial transfer. hardware per- forms address recognition after reception of the slave address and direction bit. the slave address byte is the first byte received after the master gen- erates the start condition. the slave address byte contains the 7-bit ds1340 address, which is 1101000, followed by the direction bit (r/ w ), which is 1 for a read. after receiving and decoding the slave address byte, the ds1340 outputs an acknowledge on sda. the ds1340 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. the ds1340 must receive a not acknowledge to end a read. a xxxxxxxx a 1101000 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s ?start a ?acknowledge p ?stop r/w ?read/write or direction bit address = d0h data transferred (x + 1 bytes + acknowledge) figure 8. slave receiver mode (write mode) a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s ?start a ?acknowledge p ?stop a ?not acknowledge r/w ?read/write or direction bit address = d0h data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a not acknowledge (a) signal figure 9. slave transmitter mode (read mode
handling, pc board layout, and assembly the ds1340c package contains a quartz tuning-fork crystal. pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. exposure to reflow is limited to 2 times maximum. ultrasonic cleaning should be avoided to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all n.c. (no connect) pins must be connect- ed to ground. the leaded 16-pin so package may be reflowed as long as the peak temperature does not exceed 240?. peak reflow temperature ( 230?) duration should not exceed 10 seconds, and the total time above 200? should not exceed 40 seconds (30 seconds nominal). the rohs and lead-free/rohs packages may be reflowed using a reflow profile that complies with jedec j-std-020. moisture-sensitive packages are shipped from the facto- ry dry-packed.handling instructions listed on the pack- age label must be followed to prevent damage during reflow. refer to the ipc/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. ds1340 i 2 c rtc with trickle charger ____________________________________________________________________ 13 1 2 3 4 8 7 6 5 v cc ft/out scl sda v backup gnd x2 x1 top view ds1340 so, sop ds1340c 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 scl sda gnd v backup n.c. n.c. n.c. n.c. n.c. so (300 mils) ft/out v cc n.c. n.c. n.c. n.c. n.c. pin configurations
ds1340 i 2 c rtc with trickle charger maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. pac ka ge information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip information transistor count: 10,930 process: cmos substrate connected to ground thermal information theta-ja: +170?/w (0.150in so) theta-jc: +40?/w (0.150in so) theta-ja: +221?/w (?op) theta-jc: +39?/w (?op) theta-ja: +89.6?/w (0.300in so) theta-jc: +24.8?/w (0.300in so) package document number 8-pin so (150 mils) 56-g2008-001 16-pin so (300 mils) 56-g2018-001 8-pin ?op 56-g4009-001

▲Up To Search▲

Price & Availability of DS1340Z-3TAMPR

	To Download DS1340Z-3TAMPR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .